ARM Architecture or Advanced RISC Machine has become one of the most used computer architectures in the world due to its low consumption of energy, its high performance in dealing with small and multiple tasks simultaneously, its low cost, and its small size . It is largely used in smartphones, tablets, microcomputers, and embedded systems. It has become a strong alternative for supercomputers needed for data centers because it is a power-efficient solution.
If we look around us, we will find that ARM processors are everywhere. They are always with us. However, the real motivation is that ARM processors are the future of technology. The world is going toward a green and clean technology. A technology that has a high performance, but on the other hand it respects environment. These two features are the main goal behind ARM processors. In addition, they widely used in Internet of Things which is growing and changing the view of the world about technology. And one of the growing applications of IoT is smart homes. Thus, the motivation to learn about ARM Architecture can be seen as personal to develop our own projects or global to save the planet.
Development of the ARM Architecture
Overview of the History of ARM:
The origin of ARM Architecture came from the British technology Acorn Computers which developed ARM or Acorn RISC Machine in 1980s. It was a result of success between Acorn Computers an British Broadcasting Corporation. The first ARM version was ARM1 produced in 1985. After that, ARM Holdings transformed it to Advanced RISC Machine. ARM Holdings is a British company founded in 1990. It does not make the processors themselves. Instead, it designs multicore architectures and microprocessors.
Development Road Map:
ARM has several families depending on the the ARM version from ARMv1 to ARMv8-A. The difference in version can depend on the performance, the field of use, or sometimes the manufacturer because as mentioned before ARM Holdings does not produce processors, but they make their design and architecture and give manufacturing licence to companies such as Snapdragon and Qualcomm. For instance, Cortex-M/R/A(32-bit) are under the umbrella of ARMv7 family. In this presentation, we will focus on Cortex-A/A50 family.
ARM Architecture Profiles
ARM Architecture has three main profiles. They differ in the application of the architecture in real life. First, application profile which is implemented in ARMv7-A, for instance, which includes Cortex-A/A50 family that has several features such as MMS (Memory Management Support), high performance at low power which depends on multitasking done by the operating system. Second, real time profile which is needed in embedded systems. It is implemented in ARMv7-R, for instance, which includes Cortex-R family. It has features such as protected memory and low latency and predictability “real-time” needs. Third, microcontroller profile is implemented in ARMv7-M, for instance, which includes Cortex-M family. It has features such as the deep embedded use, lowest gate entry point, and deterministic/ predictable behavior as a key element.
For ARM Architecture, Halfword means 16 bits (two bytes), Word means 32 bits (four bytes), and Doubleword means 64 bits (eight bytes). Most ARM architecture implement two instruction sets the 32-bit ARM Instruction Set and 16-bit Thumb instruction set. The Latest ARM cores such as ARMv8-A which includes Cortex-A family introduce a new instruction set called Thumb-2. It provides a mixture of 32-bit and 16-bit instructions. In addition, some new ARM cores like Cortex-A57 supports 64-bit instructions. They maintain code density with increased flexibility. Jazelle-DBX cores can also execute Java bytecode. For ARM instruction set, all instructions are 32-bit long, and they support many execution in a single cycle. They are conditionally executed. For Thumb instruction set, it is a 16-bit instruction set. It is used to optimize code density from C code (65% of ARM code size) in order to improve performance for narrow memory. It is targeted at compiler generation, so it is independent from hand coding. For Thumb-2 instruction set, it is designed to keep ARM performance and combine it with Thumb code density. In addition to 16-bit instruction set, it adds a 32-bit instruction set to implement almost all ARM functionalities.
For data processing, the available operations in ARM Architecture in Cortex-A8 are:
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons: CMP CMN TST TEQ
Data movement: MOV MVN
They interact just with register, so they do not deal with memory. The second operand in ARM uses an additional register called Barrel Shifter before ALU.
The ARM has seven basic operating modes:
- User : unprivileged mode under which most tasks run
- FIQ : entered when a high priority (fast) interrupt is raised
- IRQ : entered when a low priority (normal) interrupt is raised
- Supervisor : entered on reset and when a Software Interrupt instruction is executed
- Abort : used to handle memory access violations
- Undef : used to handle undefined instructions
- System : privileged mode using the same registers as user mode
- Monitor: a secure mode for TrustZone.
ARM Register Set
ARM has 37 registers that are 32-bits long each. Registers R0 through R7 are the same across all CPU modes; they are never banked. Registers R8 through R12 are the same across all CPU modes except FIQ mode. FIQ mode has its own distinct R8 through R12 registers.
R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.
R13 is also referred to as SP, the Stack Pointer, R14 is also referred to as LR, the Link Register, and R15 is also referred to as PC, the Program Counter.
The Program Status Register has the following 32 bits.
- M (bits 0–4) is the processor mode bits.
- T (bit 5) is the Thumb state bit.
- F (bit 6) is the FIQ disable bit.
- I (bit 7) is the IRQ disable bit.
- A (bit 8) is the imprecise data abort disable bit.
- E (bit 9) is the data endianness bit.
- IT (bits 10–15 and 25–26) is the if-then state bits.
- GE (bits 16–19) is the greater-than-or-equal-to bits.
- DNM (bits 20–23) is the do not modify bits.
- J (bit 24) is the Java state bit.
- Q (bit 27) is the sticky overflow bit.
- V (bit 28) is the overflow bit.
- C (bit 29) is the carry/borrow/extend bit.
- Z (bit 30) is the zero bit.
- N (bit 31) is the negative/less than bit.
When an exception occurs, the ARM:
- Copies CPSR into SPSR_<mode>
- Sets appropriate CPSR bits
- Change to ARM state
- Change to exception mode
- Disable interrupts (if appropriate)
- Stores the return address in LR_<mode>
- Sets PC to vector address
To return, exception handler needs to:
- Restore CPSR from SPSR_<mode>
- Restore PC from LR_<mode>
The ARM7TDMI uses a 3-stage pipeline in order to increase the speed of the flow of instructions to the processor. It allows several operations to happen simultaneously . FETCH is first stage of pipeline where the instruction is fetched from memory. Then, DECODE which is about decoding the registers used in the instruction. Finally, EXECUTE where registers read from Register Bank Shift and ALU operation and write registers back to Register Bank.
ARM Architecture is one of the the most promising technologies that every computer scientists should know about. It is used everywhere around us. In this presentation, we focused on Cortex-A family which is an application profile. It is used in smartphones because of it is low consumption of energy. We choose it because it supports 32-bit and 64-bit architectures which is a new step in ARM architecture’s history. It is the step that allowed famous companies such as Apple and Samsung to support 64-bit operating systems in their mobile phones and also 64-bit operating systems in Raspberry Pi in order to increase its use in building green data centers.
ARM – Architecture Reference Manual http://www.arm.com/.
ARM Architecture A8 Presentation Slides. http://www.arm.com/files/pdf/ARM_Arch_A8.pdf
Cortex-A Series Processors. https://developer.arm.com/products/processors/cortex-a
P. Dutta, Electrical Engineering Teaching Slides, Electrical Engineering and Computer Science Departement, University of Michigan. https://web.eecs.umich.edu/~prabal/teaching/eecs373-f11/readings/ARM_Architecture_Overview.pdf
- Stallings, Computer Organization and Architecture: Designing for Performance.